The cuBLASLt API (starting with CUDA 10.1) The cuBLASXt API (starting with CUDA 6.0), and The cuBLAS API, which is simply called cuBLAS API in this document (starting with CUDA 6.0), The cuBLAS Library exposes three sets of API: It allows the user to access the computational resources of NVIDIA Graphics Processing Unit (GPU). The cuBLAS library is an implementation of BLAS (Basic Linear Algebra Subprograms) on top of the NVIDIA®CUDA™ runtime. With the combined effort of VP lane-based PG and thread fusion, compared to a conventional VP without the two proposed capabilities, benchmarking shows that the new prototype yields up to 33.8% energy reduction in addition to 40% runtime improvement, or up to 62.7% reduction in the product of energy and runtime.The API Reference guide for cuBLAS, the CUDA Basic Linear Algebra Subroutine library. Based on an accurate power model of the VP prototype, two different policies are proposed to dynamically choose the optimal number of active VP lanes. Once thread fusion is triggered, every vector instruction issued to the virtualized VP is interpreted as two similar instructions working in two independent virtual spaces, thus doubling the vector instruction issue rate. The VP is capable of dynamically triggering thread fusion according to the availability of similar threads in the task queue. The third part of this dissertation focuses on combining the two aforementioned technologies to create an improved VP prototype that is fully virtualized to support thread fusion and dynamic lane-based power-gating (PG). Simulations of various low utilization benchmarks show that, with the proposed scheduler and power gating, the virtualized VP yields a larger than 3-fold speedup while the reduction in the total energy consumption approaches 40% compared to the same VP running in the single-threaded mode. A throughput-driven scheduler is proposed to optimize the virtualized VP’s utilization in dynamic environments where diverse threads are created randomly. The virtualization technique is applied to a multithreaded VP prototyped on an FPGA it supports VP sharing as well as power gating for better energy efficiency. With a vector register file (VRF) virtualization technique invented to dynamically allocate physical vector registers to threads, the virtualization approach improves programmer productivity by providing at run time a distinct physical register name space to each competing thread, thus eliminating the need to solve register name conflicts statically. The proposed VP virtualization technology, when applied, improves aggregate VP utilization by enabling simultaneous execution of multiple threads of similar or disparate vector lengths on a multithreaded VP. ![]() An easy-to-implement VP virtualization technology is presented to improve the VP in terms of utilization and energy efficiency. The second part of this dissertation deals with vector processors (VPs) which are commonly assigned exclusively to a single thread/core, and are not often performance and energy efficient due to mismatches with the vector needs of individual applications. Benchmarking using an FPGA prototype shows a 6-11% reduction in dynamic power dissipation as well as a 17-45% decrease in code size with frequent performance improvements due to higher instruction cache hit rates. Instruction fusion is applied to a MIPS-based dual-core that resembles an ideal multiscalar of degree two. Instruction fusion applied to vector code enables the processor to idle early pipeline stages and instruction caches at various times during program implementation with minimum performance degradation, while reducing the program size and the required instruction memory bandwidth. With instruction fusion, similar copies of an instruction to be run on multiple pipelines or cores are merged into a single copy for simultaneous execution. To alleviate its impact, an instruction fusion technique is first proposed for multiscalar and many-core processors. The utilization wall, caused by the breakdown of threshold voltage scaling, hinders performance gains for new generation microprocessors.
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